Isscc 2007 / Session 15 / Multimedia and Parallel Signal Processors

Real-time 3D graphics have been widely adopted on handheld devices such as cellular phones and PDAs with high performance processors consuming only limited power [1-3]. Recently, a vertex shader of 120Mvertices/s and 106mW at 60fps was presented [3], but it consumed a large silicon area of 1.5M transistors to integrate 16 floating-point multipliers for the fast matrix multiplications required. A full 3D graphics pipeline processor is presented with 141Mvertices/s vertex shader (VS) and 52.4mW power consumption at 60fps. The VS utilizes a logarithmic number system (LNS) for high speed and small area with only 968k transistors. For low power consumption, the 3 power domains of the chip are separately controlled by dynamic voltage and frequency scaling (DVFS).